1. Field of the Invention
This invention relates to an IC package having a plurality of multiterminal IC chips, such as a memory card.
2. Description of the Related Art
In recent years, as the capacities of semiconductor memories, e.g. ROM's and RAM's, have been increased, memory cards in which many IC chips for these semiconductor memories are packaged upon or within a single substrate, have been manufactured and used in a wide area of application such as games and process controls.
However, the above IC chips for semiconductor memories have each thirty to fifty connecting terminals, and these connecting terminals are common connecting terminals such as data bus terminals and control bus terminals, with the exception of some individual terminals such as a chip enable terminal. Thus there is a problem of connecting and wiring of these common connecting terminals and individual connecting terminals on a small substrate.
A conventional wiring structure will now be described with reference to the drawings:
FIG. 1 is a plan view of a conventional memory card; FIG. 2(A) is a partially plan view illustrating connecting and wiring between IC chips of the conventional memory card; and FIG. 2(B) is a partially sectional view thereof. A substrate 50 which forms a memory card 5 is a double-sided wiring board, as shown in FIG. 2(B). On an upper surface 50a, twenty IC chips denoted at A.sub.1 to A.sub.20 are bonded, and upper surface patterns "a" each shown by a solid line, bonding patterns "n" each shown by a solid circle and through-hole patterns "m" each shown by an open circle are provided. On the other hand, on a lower surface 50b, lower surface patterns "b" each shown by a dashed line are provided and connected to upper surface 50a by means of through-hole patterns "m".
As shown in FIG. 2(A), each IC chip "A" is square-shaped and one pair of opposite edges "c" and "d" are each provided with twenty connecting terminals, while the other pair of opposite edges "e" and "f" are not provided with any connecting terminal. And all the connecting terminals provided along edge "c" are common connecting terminals, and among the connecting terminals provided along edge "d", nineteen terminals are common connecting terminals and one terminal is a chip enable terminal.
Connecting and wiring between the above IC chips will be described with reference to A.sub.1, A.sub.2 and A.sub.3.
As shown in FIG. 2(A), twenty connecting terminals provided along edge c.sub.2 of IC chip A.sub.2 are connected to respective bonding patterns n.sub.2, and twenty connecting terminals provided along edge d.sub.2 are connected to respective through-hole patterns m.sub.2 each by wire bonding. In a similar way, as for IC chip A.sub.3, connecting terminals along edge c.sub.3 are connected to respective bonding patterns n.sub.3, and connecting terminals along edge d.sub.3 are connected to respective through-hole patterns m.sub.3 each by wire bonding. Half (ten in number) of bonding patterns n.sub.2 connected to connecting terminals of IC chip A.sub.2 are connected to respective bonding patterns n.sub.3 connected to the common connecting terminals of IC chip A.sub.3, by means of ten upper surface patterns a.sub.1 which are arranged on the upper part of IC chip A.sub.2 so as to avoid through-hole patterns m.sub.2, and the remaining bonding patterns n.sub.2 are connected to the corresponding bonding patterns of IC chip A.sub.3 by means of ten upper surface patterns a.sub.2 which are arranged on the lower part of IC chip A.sub.2. Furthermore through-hole patterns m.sub.2 connected to connecting terminals of IC chip A.sub.2, are directly connected to through-hole patterns m.sub.3 of IC chip A.sub.3 by means of lower surface patterns "b" arranged on the lower surface of substrate 50.
That is to say, the above-mentioned structure allows connections between common connecting terminals which are provided along one edge of each IC chip to be made on upper surface 50a to which IC chips are bonded. On lower surface 50b where no IC chip exists, connections between common connecting terminals provided along the other edge of each IC chip are made, and at the same time the wiring of each individual connecting terminal is separately made all over the surface.
The above is the connection structure between the respective IC chips. Next, the entire connection structure will be described with reference to FIG. 1.
That is to say, twenty IC chips A.sub.1 to A.sub.20 are arranged and bonded in four rows in the arrangement direction of IC chips on substrate 50, as shown by arrow B. At this time, by reversing the direction of IC chips every row, as shown by arrows in the IC chips, the IC chips can be connected on the same plane without crossing the connections between IC chips throughout each of rows.
As mentioned above, the conventional memory card is designed so that many IC chips are directly packaged on a single circuit board. Therefore, wiring between common connecting terminals must be divided into the upper surface and the lower surface of the substrate. As a result, since the circuit board needs a lot of through-hole patterns and high-density wiring patterns, there are problems of increased costs caused by a costly process for making through-hole patterns and of decreased yields caused by high-density packaging of IC chips onto high-density wiring patterns.
On the other hand, by use of a single-sided print board, it is possible to make all connections between common connecting terminals on the IC chip bonding surface, but this requires considerably wide wiring space on both sides of an IC chip, and therefore, it is necessary to make an arrangement, with the distance between IC chips kept long. As a result, there causes a problem that the number of IC chips being mountable on a single card is limited.
The object of the present invention is to provide an IC package which is free of the above problems, low in cost and has a high packaging density.